wangdequan/linuxcncWebWASM
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Implement AXIS parity UI and execution baseline

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wangdequan
2026-08-23 07:28:37 +08:00
parent 1325504544
commit 06f96f85e5
463 changed files with 84893 additions and 692 deletions
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31
wasm-core/tests/sim_interpreter_test.c
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@@ -6,6 +6,7 @@
int main(void) {
sim_interpreter interpreter = {0};
sim_interpreter parameter_interpreter = {0};
sim_interpreter_state state = {0};
sim_interpreter_state second = {0};
char canonical[SIM_INTERPRETER_CANONICAL_CAPACITY] = {0};
@@ -18,6 +19,23 @@ int main(void) {
required = sim_interpreter_canonical(&interpreter, canonical, sizeof(canonical));
assert(required > 1 && canonical[required - 1] == '\0');
assert(sim_interpreter_state_hash(&interpreter) != 0);
assert(sim_interpreter_modal_hash(&interpreter) != 0);
assert(sim_interpreter_size() == sizeof(sim_interpreter));
assert(sim_interpreter_init(&parameter_interpreter) == SIM_INTERP_OK);
assert(sim_interpreter_execute(&parameter_interpreter, "#1=10 #2=[#1*2+5] X[#2/5]", (uint32_t)(sizeof("#1=10 #2=[#1*2+5] X[#2/5]") - 1)) == SIM_INTERP_OK);
assert(fabs(parameter_interpreter.state.x - 5.0) < 1e-12);
{
double parameter = 0.0;
assert(sim_interpreter_parameter_get(&parameter_interpreter, 2, &parameter) == SIM_INTERP_OK);
assert(fabs(parameter - 25.0) < 1e-12);
}
assert(sim_interpreter_parameter_set(&parameter_interpreter, 5399, 12.5) == SIM_INTERP_OK);
assert(sim_interpreter_execute(&parameter_interpreter, "#100=[#5399+1] X[#100]", (uint32_t)(sizeof("#100=[#5399+1] X[#100]") - 1)) == SIM_INTERP_OK);
assert(fabs(parameter_interpreter.state.x - 13.5) < 1e-12);
assert(sim_interpreter_parameter_set(&parameter_interpreter, 5400, 1.0) == SIM_INTERP_ERR_PARAMETER);
assert(sim_interpreter_execute(&parameter_interpreter, "G1 X?", 5) == SIM_INTERP_ERR_SYNTAX);
assert(sim_interpreter_error_column(&parameter_interpreter) == 4);
assert(sim_interpreter_error_code(&parameter_interpreter) == SIM_INTERP_ERR_SYNTAX);
assert(sim_interpreter_execute(&interpreter, "G91 X1 (increment)", (uint32_t)(sizeof("G91 X1 (increment)") - 1)) == SIM_INTERP_OK);
assert(sim_interpreter_read_state(&interpreter, &second) == SIM_INTERP_OK);
assert(second.x == 11.0 && second.line == state.line + 1);
@@ -32,5 +50,18 @@ int main(void) {
assert(sim_interpreter_execute(&interpreter, "M2", 2) == SIM_INTERP_OK);
assert(interpreter.state.program_end == 1);
assert(sim_interpreter_execute(&interpreter, "G1 X0", (uint32_t)(sizeof("G1 X0") - 1)) == SIM_INTERP_ERR_STATE);
assert(sim_interpreter_reset(&interpreter) == SIM_INTERP_OK);
assert(sim_interpreter_execute(&interpreter, "G10 L2 P1 X10 Y20 Z30", (uint32_t)(sizeof("G10 L2 P1 X10 Y20 Z30") - 1)) == SIM_INTERP_OK);
assert(sim_interpreter_execute(&interpreter, "G54 G90 X1 Y2 Z3", (uint32_t)(sizeof("G54 G90 X1 Y2 Z3") - 1)) == SIM_INTERP_OK);
assert(fabs(interpreter.state.x - 11.0) < 1e-12);
assert(fabs(interpreter.state.y - 22.0) < 1e-12);
assert(fabs(interpreter.state.z - 33.0) < 1e-12);
assert(sim_interpreter_reset(&interpreter) == SIM_INTERP_OK);
assert(sim_interpreter_execute(&interpreter, "G54 G43 H12 G81 X1 Y2 Z-3 R1", (uint32_t)(sizeof("G54 G43 H12 G81 X1 Y2 Z-3 R1") - 1)) == SIM_INTERP_OK);
assert(interpreter.state.motion_mode == 1);
assert(sim_interpreter_modal_hash(&interpreter) != 0);
assert(sim_interpreter_execute(&interpreter, "G80 M7", (uint32_t)(sizeof("G80 M7") - 1)) == SIM_INTERP_OK);
assert(sim_interpreter_execute(&interpreter, "M8", 2) == SIM_INTERP_OK);
assert(sim_interpreter_execute(&interpreter, "M9", 2) == SIM_INTERP_OK);
return 0;
}